A Noise-Tolerant Dynamic Circuit Design Technique
نویسنده
چکیده
A new circuit technique, referred to as the twin-transistor technique, for increasing the noise immunity of dynamic logic circuits is presented. This technique makes dynamic logic gates more tolerant to noise appearing at the gate inputs. A multiply-accumulate circuit has been designed and fabricated using a 0.35pm process to veri f y this technique. Experimental results indicate that the twin-transistor technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4X) with only a modest increase in power dissipation ( I f l o ) and no loss in throughput.
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